Computer Science 代写:数字信号处理器
DSP or Digital Signal Processor is the part of the TMS320C6x (C6X) family, is the microprocessors with speedy function and appropriate with instruction set and architecture for the purpose of digital signaling. DSP techniques are treated as the most successful real time signal processing and powerful processor of the C6X group as it is made in such a way that it is most helpful for numerically intensive calculation .DSP’s base is VLIW architecture or very long instruction word. The internal memory of DSP is in that way that eight instruction can be fetched in every single cycle.
Digital signal processors are used within a huge range of applications including communications and it controls the speech and image processing too.”DSP is concerned with the representation of discrete time signal by a sequence of numbers or symbols and the processing of these signals. Digital signal processing and signal analog signal processing are subfields of signal processing. DSP includes subfields like: speech and audio signal processing, radar and sonar signal processing, sensor array processing, spectral estimation, statistical signal processing, digital image signal processing signal processing for communications, control of systems, biomedical signal processing, seismic data processing etc”.
Areas where it generally uses-In cell phones, fax/modems, disk drives, radio, printers, HD, iPods, iPads, digital cameras etc .the reason why DSP uses in wide number is it is very much cost effective. As we said earlier that DSP is a real time signal processing it requires some external pace along with analog input .in high frequency range though DSP is not very useful but in case of audio-frequency range it is more comfortable. The figure given below shows the TMS320C6713 DSK-
Input can be sampled at 8 kHz, and by sampling we figure that each value which is sampled by the processor, and is acquired at the rate of 1/ (sampling rate) or it also means that every value is being sampled every 1/(sampling rate) sec. However if we use a sampling rate of 8 kHz, then the processor will gain the values at every 1/ (8*10^3) seconds or 0.125 milliseconds. The rate of sampling for a compact disc is 44.1 kHz and analog signals which can also be sampled at 48 kHz depending upon the needs of the application.
Digital signal Processing and applications with the C6713 And C6416 DSK by Rulph Chassaing, 2005.
The typical or common DSP application goes in the following manner
System of communication
Demodulation and demodulation, channel of
equalization, cancellation of echo
Electronic and consumer
Audio and video coding in way of perptual
DVDs, speech synthesis, recognition of speech.
Instruments made of synthetic, effects of audio
Reduction of noise
ECG, EEG, MEG, AED, audiology etc.
seismology, exploration of oil
speckle interferometry and VLWI
Evaluation of sensor data
Radar and its navigation
biometric identification etc.
System control,extraction of features
The DSK board is not expensive one and it’s the advantage of applying DSP.
TheDSP on the 6713 DSK integreted to the on-board integral part by a 32-bit wide EMIF or External Memory InterFace.The SDRAM, Flash and CPLD all there are connected to the bus. EMIF signals are also connected along with the daughter card expansion connectors which are generally used for third party add-in boards.DSP interfaces to the analog audio signs through the on-board AIC23 codec and four 3.5 mm audio related jacks that are microphone input, line output, line input, and headphone output.The codec can pick the microphone or the line input as the active input. The analog output is advanced to the both of the headphone which is adjustable gain and line output that is fixed gained and connectors. To send commands to the codec control interface while McBSP0 is applied. McBSP1 is applied for the gained digital audio data. McBSP0 and McBSP1 may be re-routed to the expansion connectors in the software.CPLD is a programmable logic device used to implement glue logic that connectsthe board components altogether. The CPLD has a register based user interface that enables the user construct the board by writing and reading to its registers.The DSK involves 4 LEDs and 4 position DIP switch as a easy process way to supply the user with interactive justification. Both are accessed by reading and writing to the CPLD registers. An included 5V external current supply is applied to power the board. On-board switching voltage regulators supplies the +1.26V DSP core voltage and +3.3V I/O supplies. The board is held in reset til these providings are within executing specifications.The C67xx family of DSPs has a lhuge byte addressable address space. Data and program code can be placed anywhere in the unified address space. Addresses are always remains as 32-bits wide.The memory map presents the address space of a generic 6713 processor on the left with particular specification of how every region is applied on the right. By default, the internal memory sits at the starting of the address space. Part of the internal memory can be constructed again in software as L2 cache rather than RAM that is fixed anyway.The EMIF has 4 different addressable regions which called chip enable spaces (CE0-CE3).The SDRAM engages CE0 where the Flash and CPLD jointly share CE1.CE2 and CE3 which are commonly reserved for the daughtercards.
Computer Science 代写:数字信号处理器